PCB design of decoupling capacitors

On the printed circuit board, the inductance of the trace connecting the decoupling capacitor to the power rail is much larger than the parasitic inductance on the capacitor. Generally speaking, the trace inductance is 10nH/in. Therefore, when installed in such a high-inductance mounting structure, the high-frequency decoupling performance of a low-inductance capacitor will be significantly reduced. The ESL of ordinary surface-mount capacitors is basically nH, and the increase in parasitic inductance caused by the wiring and pad design is much more obvious than the ESL of the capacitor itself. In today's high-frequency decoupling applications, minimizing loop inductance is also crucial. One way to minimize loop inductance is to reduce the size of the loop area. As far as the layout is concerned, it is better to move the power rail as close as possible, and even put the power rail under the IC, so that the area of u200bu200bthe loop area can be reduced. Nevertheless, for high-frequency decoupling, its performance is still limited by the inductance of the traces and power rails. By using vias in the pad, the loop inductance can be further reduced.　　In the best pad design, the main inductance is the height of the via and the capacitor. The via is like a natural inductance coil. The inductance of a via is proportional to its length and diameter. Connecting a decoupling capacitor through a 60mil circuit board through a via (8mil) can increase the inductance of 1nH. In addition, the vertical distance during current transmission will increase the size of the loop and thus increase the inductance. Optimal pad design and minimize the distance between the top of the capacitor and the power supply and ground, so that the inductance of the decoupling capacitor is reduced as it should be.