Talk about some frequently seen problems and solutions in the process of high-speed circuit board design

As the operating frequency of devices becomes higher and higher, the signal integrity problems faced by high-speed PCB design have become a bottleneck in traditional designs, and engineers are facing increasing challenges in designing complete solutions. Although relevant high-speed simulation tools and interconnection tools can help design designers solve some problems, high-speed PCB design also requires continuous accumulation of experience and in-depth exchanges between industries. Listed below are some of the issues that have received widespread attention. The influence of wiring topology on signal integrity When the signal is transmitted along the transmission line on the high-speed PCB board, signal integrity problems may occur. Netizen tongyang of STMicroelectronics asked: For a set of buses (address, data, commands) driving up to 4 or 5 devices (FLASH, SDRAM, etc.), when PCB wiring, the bus arrives at each device in turn, as first Connect to SDRAM, then to FLASH...The bus is still distributed in a star shape, that is, it is separated from some place and connected to each device. Which of the two methods is better in terms of signal integrity? In this regard, Li Baolong pointed out that the influence of wiring topology on signal integrity is mainly reflected in the inconsistent signal arrival time on each node, and the reflected signal also inconsistent when it reaches a certain node. , So the signal quality deteriorates. Generally speaking, the star topology structure can achieve better signal quality by controlling several branches of the same length to make the signal transmission and reflection delay consistent. Before using the topology, the situation of the signal topology node, the actual working principle and the wiring difficulty should be considered. Different buffers have inconsistent effects on the reflection of the signal, so the star topology cannot solve the delay of the data address bus connected to FLASH and SDRAM, and thus cannot ensure the quality of the signal; on the other hand, high-speed signals generally For communication between DSP and SDRAM, the rate of FLASH loading is not high, so in high-speed simulation, you only need to ensure the waveform at the node where the actual high-speed signal works effectively, without paying attention to the waveform at FLASH; star topology compares daisy chain and other topologies. In other words, wiring is more difficult, especially when a large number of data address signals use star topology. The impact of pads on high-speed signals In a PCB, from a design point of view, a via is mainly composed of two parts: the middle hole and the pad around the hole. An engineer named fulonm asked the guest about the impact of pads on high-speed signals. In this regard, Li Baolong said: pads have an impact on high-speed signals, and it affects the impact of similar device packaging on devices. A detailed analysis shows that after the signal comes out of the IC, it passes through the bonding wire, pins, package shell, pad, and solder to the transmission line. All joints in this process will affect the quality of the signal. But in actual analysis, it is difficult to give the specific parameters of the pad, solder and pin. Therefore, the package parameters in the IBIS model are generally used to summarize them. Of course, such analysis can be received at lower frequencies, but it is not accurate enough for higher frequency signals to simulate with higher precision. A current trend is to use IBIS's V-I and V-T curves to describe the buffer characteristics, and use the SPICE model to describe the packaging parameters. How to suppress electromagnetic interference PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to the electromagnetic compatibility (EMC) of electronic products. If emphasizing EMC/EMI in high-speed circuit board proofing, it will help shorten the product development cycle and speed up the time to market. Therefore, many engineers are very concerned about the problem of suppressing electromagnetic interference in this forum. For example, Shu Jian of Wuxi Xiangsheng Medical Imaging Co., Ltd. said that the harmonics of the clock signal were found to be very serious in the EMC test. Is it necessary to perform special treatment on the power supply pins of the IC that uses the clock signal? Connect a decoupling capacitor to the power supply pin. In the PCB design, which aspects should be paid attention to to suppress electromagnetic radiation? In this regard, Li Baolong pointed out that the three elements of EMC are radiation source, transmission route and victim. The propagation path is divided into space radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power decoupling is to solve the propagation of conduction mode. In addition, necessary matching and shielding are also required.